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LXT972 3.3v dual-speed fast ethernet transceiver february 2000 data sheet general description features revision 1.1 refer to www.level1.com for most current information. ) the LXT972 is an ieee compliant fast ethernet phy transceiver that directly supports both 100base-tx and 10base-t applications. it provides a media independent interface (mii) for easy attachment to 10/100 media access controllers (macs). the LXT972 supports full-duplex operation at 10 mbps and 100 mbps. its operating condition can be set using auto-negotiation, parallel detection, or manual control. the LXT972 is fabricated with an advanced cmos process and requires only a single 3.3v power supply. applications ? combination 10base-t/100base-tx network interface cards (nics) ? 10/100 pcmcia cards ? cable modems and set-top boxes ? 3.3v operation. ? low power consumption (300 mw typical). ? 10base-t and 100base-tx using a single rj-45 connection. ? supports auto-negotiation and parallel detection. ? mii interface with extended register capability. ? robust baseline wander correction performance. ? standard csma/cd or full-duplex operation. ? configurable via mdio serial port or hardware control pins. ? integrated, programmable led drivers. ? 64-pin low-profile quad flat package (lqfp). ? LXT972lc - commercial (0 to 70 c ambient). tx_en rx_er crs pwr supply management / mode select logic addr0 mdio mdc mdint tx_er rxdv tpon tpop tpin tpip refclk vcc gnd col rx_clk tx_clk reset led/cfg <3:1> txd <3:0> decoder & descrambler + - serial-to- parallel converter scrambler & encoder parallel/serial converter carrier sense data valid error detect auto negotiation manchester decoder manchester encoder 10 100 10 100 media select tp driver tp out register set register set clock generator + - 10bt collision detect clock generator tx pcs osp ? adaptive eq with baseline wander cancellation osp ? slicer osp ? pulse shaper rxd<3:0> + - 100tx tp in mddis txslew<1:0> rx pcs pwrdwn jtag tdi, tdo, tms, tck, trst LXT972 block dia g ram
LXT972 3.3v dual-speed fast ethernet transceiver 2 table of contents pin assignments .........................................................4 signal descriptions ......................................................6 functional description ..............................................10 introduction ...............................................................10 osp? architecture ................................................10 comprehensive functionality ................................11 network media/protocol support ........................11 10/100 network interface ......................................11 twisted-pair interface .......................................11 fault detection and reporting ........................11 remote fault ................................................11 mii data interface ...................................................12 configuration management interface ..................12 mdio management interface ..........................12 mdio addressing ........................................12 mdio frame structure ...............................12 mii interrupts ......................................................13 hardware control interface .............................13 operating requirements ........................................14 power requirements ..............................................14 clock requirements ...............................................14 external crystal oscillator ...............................14 initialization ...............................................................14 mdio control mode ................................................14 hardware control mode .........................................14 reduced power modes ..........................................15 hardware power down ....................................15 software power down ......................................15 reset .........................................................................15 hardware configuration settings .........................16 establishing link .....................................................17 auto-negotiation .....................................................17 base page exchange .......................................17 next page exchange ........................................17 controlling auto-negotiation ...........................17 parallel detection ....................................................17 mii operation .............................................................18 mii clocks .................................................................18 transmit enable ......................................................18 receive data valid ..................................................18 carrier sense ...........................................................18 error signals ............................................................18 collision ....................................................................18 loopback ..................................................................20 operational loopback ......................................20 test loopback ....................................................20 100 mbps operation ................................................21 100base-x network operation ...........................21 collision indication ..................................................24 100base-x protocol sublayer operations .........25 pcs sublayer ....................................................25 preamble handling ......................................25 dribble bits ...................................................25 4b/5b coding table ..........................................26 pma sublayer ....................................................27 link ................................................................27 link failure override ...................................27 carrier sense ...............................................27 receive data valid ......................................27 twisted-pair pmd sublayer .............................27 scrambler/descrambler ..............................27 baseline wander correction ......................27 polarity correction .......................................27 programmable slew rate control ............27 10 mbps operation ..................................................28 10t preamble handling .........................................28 10t carrier sense ...................................................28 10t dribble bits .......................................................28 10t link integrity test ............................................28 link failure .........................................................28 10t sqe (heartbeat) .............................................28 10t jabber ...............................................................28 10t polarity correction ..........................................28
LXT972 table of contents 3 monitoring operations ........................................... 29 monitoring auto-negotiation ................................. 29 monitoring next page exchange .................... 29 led functions ......................................................... 29 led pulse stretching ....................................... 30 boundary scan (jtag) functions ...................... 31 boundary scan interface ....................................... 31 state machine ......................................................... 31 instruction register ................................................ 31 boundary scan register (bsr) ............................ 31 application information ............................................ 32 magnetics information ............................................ 32 typical twisted-pair interface ............................... 34 typical mii interface ............................................... 35 preliminary test specifications .............................. 36 electrical parameters ............................................. 36 absolute maximum ratings .................................. 36 operating conditions ............................................. 36 digital i/o characteristics ...................................... 37 digital i/o characteristics - mii pins .................... 37 i/o characteristics - refclk/xi and xo pins .. 37 i/o characteristics - led/cfg pins .................... 38 100base-tx transceiver characteristics .......... 38 10base-t transceiver characteristics ............... 38 10base-t link integrity timing characteristics 39 timing diagrams ..................................................... 40 100base-tx receive timing - 4b mode .......... 40 100base-tx transmit timing - 4b mode ......... 41 10base-t receive timing .................................... 42 10base-t transmit timing ................................... 43 10base-t jab and unjab timing ........................ 44 auto negotiation and fast link pulse timing .... 45 mdio timing ............................................................ 46 power-up timing .................................................... 47 reset pulse width and recovery timing ........ 47 register definitions ................................................... 48 control register (address 0) ................................ 51 status register (address 1) .................................. 52 phy identification register 1 (address 2) .......... 53 phy identification register 2 (address 3) .......... 53 a/n advertisement register (address 4) ............ 54 a/n link partner ability register (address 5) .... 55 a/n expansion register (address 6) ..............................................................56 a/n next page transmit register (address 7) ..57 a/n link partner next page receive register (address 8) ..............................................................57 port configuration register (address 16) ...........58 quick status register (address 17) ....................59 interrupt enable register (address 18) ...............60 interrupt status register (address 19) ................61 led configuration register (address 20) ..........62 transmit control register (address 30) ..............64 package specifications ............................................65 revision history .........................................................66
LXT972 3.3v dual-speed fast ethernet transceiver 4 pin assignments figure 1: 64-pin lqfp pin assignments LXT972 rxd0 rbias 17 64 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 refclk/xi xo mddis reset txslew0 txslew1 gnd vccio n/c n/c gnd addr0 gnd gnd gnd gnd 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 gnd tpop tpon vcca vcca tpip tpin gnd gnd tdi tdo tms tck trst gnd 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 rxd1 rxd2 rxd3 n/c mdc mdio gnd vccio pwrdwn led/cfg1 led/cfg2 led/cfg3 test1 test0 pause mdint crs col gnd txd3 txd2 txd1 txd0 tx_en tx_clk tx_er rx_er rx_clk vccd gnd rx_dv 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 )
LXT972 pin assignments 5 table 1: lqfp numeric pin list pin symbol type reference for full description 1. refclk/xi input table 4 on page 8 2. xo output table 4 on page 8 3. mddis input table 2 on page 6 4. reset input table 4 on page 8 5. txslew0 input table 4 on page 8 6. txslew1 input table 4 on page 8 7. gnd C table 5 on page 9 8. vccio C table 5 on page 9 9. n/c C table 4 on page 8 10. n/c C table 4 on page 8 11. gnd C table 5 on page 9 12. addr0 input table 4 on page 8 13. gnd C table 5 on page 9 14. gnd C table 5 on page 9 15. gnd C table 5 on page 9 16. gnd C table 5 on page 9 17. rbias analog input table 4 on page 8 18. gnd C table 5 on page 9 19. tpop output table 3 on page 7 20. tpon output table 3 on page 7 21. vcca C table 5 on page 9 22. vcca C table 5 on page 9 23. tpip input table 3 on page 7 24. tpin input table 3 on page 7 25. gnd C table 5 on page 9 26. gnd C table 5 on page 9 27. tdi input table 6 on page 9 28. tdo output table 6 on page 9 29. tms input table 6 on page 9 30. tck input table 6 on page 9 31. trst input table 6 on page 9 32. gnd C table 5 on page 9 33. pause input table 4 on page 8 34. test0 input table 4 on page 8 35. test1 input table 4 on page 8 36. led/cfg3 i/o table 7 on page 9 37. led/cfg2 i/o table 7 on page 9 38. led/cfg1 i/o table 7 on page 9 39. pwrdwn input table 4 on page 8 40. vccio C table 5 on page 9 41. gnd C table 5 on page 9 42. mdio i/o table 2 on page 6 43. mdc input table 2 on page 6 44. n/c C table 4 on page 8 45. rxd3 output table 2 on page 6 46. rxd2 output table 2 on page 6 47. rxd1 output table 2 on page 6 48. rxd0 output table 2 on page 6 49. rx_dv output table 2 on page 6 50. gnd C table 5 on page 9 51. vccd C table 5 on page 9 52. rx_clk output table 2 on page 6 53. rx_er output table 2 on page 6 54. tx_er input table 2 on page 6 55. tx_clk output table 2 on page 6 56. tx_en input table 2 on page 6 57. txd0 input table 2 on page 6 58. txd1 input table 2 on page 6 59. txd2 input table 2 on page 6 60. txd3 input table 2 on page 6 61. gnd C table 5 on page 9 62. col output table 2 on page 6 63. crs output table 2 on page 6 64. mdint open drain table 2 on page 6 table 1: lqfp numeric pin list C continued pin symbol type reference for full description
LXT972 3.3v dual-speed fast ethernet transceiver 6 signal descriptions table 2: LXT972 mii signal descriptions lqfp pin# symbol type 1 signal description data interface pins 60 59 58 57 txd3 txd2 txd1 txd0 i transmit data . txd is a bundle of parallel data signals that are driven by the mac. txd<3:0> shall transition synchronously with respect to the tx_clk. txd<0> is the least significant bit. 56 tx_en i transmit enable . the mac asserts this signal when it drives valid data on txd. this signal must be synchronized to tx_clk. 55 tx_clk o transmit clock . tx_clk is sourced by the phy in both 10 and 100 mbps operations. 2.5 mhz for 10 mbps operation, 25 mhz for 100 mbps operation. 45 46 47 48 rxd3 rxd2 rxd1 rxd0 o receive data . rxd is a bundle of parallel signals that transition synchronously with respect to the rx_clk. rxd<0> is the least significant bit. 49 rx_dv o receive data valid . the LXT972 asserts this signal when it drives valid data on rxd. this output is synchronous to rx_clk. 53 rx_er o receive error . signals a receive error condition has occurred. this output is synchronous to rx_clk. 54 tx_er i transmit error . signals a transmit error condition. this signal must be synchronized to tx_clk. 52 rx_clk o receive clock . 25 mhz for 100 mbps operation, 2.5 mhz for 10 mbps operation. refer to clock requirements on page 14 in the functional description section. 62 col o collision detected . the LXT972 asserts this output when a collision is detected. this output remains high for the duration of the collision. this signal is asynchronous and is inactive during full-duplex operation. 63 crs o carrier sense . during half-duplex operation (bit 0.8 = 0), the LXT972 asserts this output when either transmitting or receiving data packets. during full-duplex operation (bit 0.8 = 1), crs is asserted during receive. crs assertion is asynchronous with respect to rx_clk. crs is de-asserted on loss of carrier, synchronous to rx_clk. mii control interface pins 3 mddis i management disable . when mddis is high, the mdio is disabled from read and write operations. when mddis is low at power up or reset, the hardware control interface pins con- trol only the initial or default values of their respective register bits. after the power-up/reset cycle is complete, bit control reverts to the mdio serial channel. 1. type column coding: i = input, o = output, a = analog, od = open drain.
LXT972 signal descriptions 7 43 mdc i management data clock . clock for the mdio serial data channel. maximum fre- quency is 8 mhz. 42 mdio i/o management data input/output . bidirectional serial data channel for phy/sta communication. 64 mdint od management data interrupt . when bit 18.1 = 1, an active low output on this pin indicates status change. interrupt is cleared by reading register 19. table 2: LXT972 mii signal descriptions C continued lqfp pin# symbol type 1 signal description 1. type column coding: i = input, o = output, a = analog, od = open drain. table 3: LXT972 network interface signal descriptions lqfp pin# symbol type 1 signal description 19 20 tpop tpon o twisted-pair outputs, positive & negative. during 100base-tx or 10base-t operation, tpop/n pins drive 802.3 compli- ant pulses onto the line. 23 24 tpip tpin i twisted-pair inputs, positive & negative. during 100base-tx or 10base-t operation, tpip/n pins receive differential 100base-tx or 10base-t signals from the line. 1. type column coding: i = input, o = output, a = analog, od = open drain
LXT972 3.3v dual-speed fast ethernet transceiver 8 table 4: LXT972 miscellaneous signal descriptions lqfp pin# symbol type 1 signal description 5 6 txslew0 txslew1 i tx output slew controls 0 and 1 . these pins select the tx output slew rate (rise and fall time) as follows: txslew1 txslew0 slew rate (rise and fall time) 0 0 2.5 ns 0 1 3.1 ns 1 0 3.7 ns 1 1 4.3 ns 4 reset i reset . this active low input is ored with the control register reset bit (0.15). the LXT972 reset cycle is extended to 258 m s (nominal) after reset is deas- serted. 12 addr0 i address0. sets device address. 17 rbias ai bias . this pin provides bias current for the internal circuitry. must be tied to ground through a 22.1 k w , 1% resistor. 33 pause i pause . when set high, the LXT972 advertises pause capabilities during auto negotiation. 34 test0 i test . tie low. 35 test1 i test . tie low. 39 pwrdwn i power down . when set high, this pin puts the LXT972 in a power-down mode. 1 2 refclk/xi xo i o crystal input and output . a 25 mhz crystal oscillator circuit can be con- nected across xi and xo. a clock can also be used at xi. refer to functional description for detailed clock requirements. 9, 10, 44 n/c - no connection . these pins are not used and should not be terminated. 1. type column coding: i = input, o = output, a = analog, od = open drain
LXT972 signal descriptions 9 table 5: LXT972 power supply signal descriptions lqfp pin# symbol type signal description 51 vccd - digital power. requires a 3.3v power supply. 7, 11, 13, 14, 15, 16, 18, 25, 26, 32, 41, 50, 61 gnd - ground. 8, 40 vccio - mii power. requires either a 3.3v or a 2.5v supply. must be supplied from the same source used to power the mac on the other side of the mii. 21, 22 vcca - analog power. requires a 3.3v power supply. table 6: LXT972 jtag test signal descriptions lqfp pin# symbol type 1 signal description 27 tdi 2 i test data input . test data sampled with respect to the rising edge of tck. 28 tdo 2 o test data output . test data driven with respect to the falling edge of tck. 29 tms 2 i test mode select . 30 tck 2 i test clock . test clock input sourced by ate. 31 trst 2 i test reset . test reset input sourced by ate. 1. type column coding: i = input, o = output, a = analog, od = open drain. 2. if jtag port is not used, these pins do not need to be terminated. table 7: LXT972 led signal descriptions lqfp pin# symbol type 1 signal description 38 37 36 led/cfg1 led/cfg2 led/cfg3 i/o led drivers 1 -3. these pins drive led indicators. each led can display one of several available status conditions as selected by the led configuration register (refer to table 50 on page 62 for details). configuration inputs 1-3. these pins also provide initial configuration set- tings (refer to table 8 on page 16 for details). 1. type column coding: i = input, o = output, a = analog, od = open drain
LXT972 3.3v dual-speed fast ethernet transceiver 10 functional description introduction the LXT972 is a single-port fast ethernet 10/100 transceiver that supports 10 mbps and 100 mbps networks. it complies with all applicable requirements of ieee 802.3. the LXT972 can directly drive either a 100base-tx line (up to 140 meters) or a 10base-t line (up to 185 meters). comprehensive functionality the LXT972 provides a standard media independent interface (mii) for 10/100 macs. the LXT972 performs all functions of the physical coding sublayer (pcs) and physical media attachment (pma) sublayer as defined in the ieee 802.3 100base-x standard. this device also performs all functions of the physical media dependent (pmd) sublayer for 100base-tx connections. on power-up, the LXT972 reads its configuration pins to check for forced operation settings. if not configured for forced operation, it uses auto-negotiation/parallel detection to automatically determine line operating conditions. if the phy device on the other side of the link supports auto- negotiation, the LXT972 will auto-negotiate with it using fast link pulse (flp) bursts. if the phy partner does not support auto-negotiation, the LXT972 will automatically detect the presence of either link pulses (10 mbps phy) or idle symbols (100 mbps phy) and set its operating conditions accordingly. the LXT972 provides half-duplex and full-duplex operation at 100 mbps and 10 mbps. osp? architecture level one's LXT972 incorporates high-efficiency optimal signal processing? design techniques, combining the best properties of digital and analog signal processing to produce a truly optimal device. the receiver utilizes decision feedback equalization to increase noise and cross-talk immunity by as much as 3 db over an ideal all-analog equalizer. using osp mixed-signal processing techniques in the receive equalizer avoids the quantization noise and calculation truncation errors found in traditional dsp-based receivers (typically complex dsp engines with a/d converters). this results in improved receiver noise and cross-talk performance. the osp signal processing scheme also requires substantially less computational logic than traditional dsp- based designs. this lowers power consumption and also reduces the logic switching noise generated by dsp engines. this logic switching noise can be a considerable source of emi generated on the devices power supplies. the osp-based LXT972 provides improved data recovery, emi performance and low power consumption.
LXT972 functional description 11 network media / protocol support the LXT972 supports both 10base-t and 100base-tx ethernet over twisted-pair. 10/100 network interface the network interface port consists of two differential signal pairs. refer to table 3 for specific pin assignments. the LXT972 output drivers generate either 100base-tx or 10base-t. when not transmitting data, the LXT972 generates 802.3-compliant link pulses or idle code. input signals are decoded either as a 100base-tx or 10base- t input, depending on the mode selected. auto- negotiation/parallel detection or manual control is used to determine the speed of this interface. twisted-pair interface the LXT972 supports either 100base-tx or 10base-t connections over 100 w, category 5, unshielded twisted pair (utp) cable. when operating at 100 mbps, the lxt971 continuously transmits and receives mlt3 symbols. when not transmitting data, the lxt971 generates idle symbols. during 10 mbps operation, manchester-encoded data is exchanged. when no data is being exchanged, the line is left in an idle state. link pulses are transmitted periodically to keep the link up. only a transformer, rj-45 connector, load resistor, and bypass capacitors are required to complete this interface. on the transmit side, the LXT972 has an active internal termination and does not require exter- nal termination resistors. level one's patented wave- shaping technology shapes the outgoing signal to help reduce the need for external emi filters. four slew rate settings (refer to table 4 on page 8 ) allow the designer to match the output waveform to the magnetic charac- teristics. on the receive side, the internal impedance is high enough that it has no practical effect on the exter- nal termination circuit. fault detection and reporting the LXT972 supports one fault detection and reporting mechanism. remote fault refers to a mac-to-mac communication function that is essentially transparent to phy layer devices. it is used only during auto-negotiation, and therefore is applicable only to twisted-pair links. far-end fault, on the other hand, is an optional pma-layer function that may be embedded within phy devices. the LXT972 supports only the remote fault function, explained in the paragraph that follows. remote fault bit 4.13 in the auto-negotiation advertisement register is reserved for remote fault indications. it is typically used when re-starting the auto-negotiation sequence to indicate to the link partner that the link is down because the advertising device detected a fault. when the LXT972 receives a remote fault indication from its partner during auto-negotiation it: ? sets bit 5.13 in the link partner base page ability register, and ? sets the remote fault bit 1.4 in the mii status register to pass this information to the local con- troller.
LXT972 3.3v dual-speed fast ethernet transceiver 12 mii data interface the LXT972 supports a standard media independent interface (mii). the mii consists of a data interface and a management interface. the mii data interface passes data between the LXT972 and a media access controller (mac). separate parallel buses are provided for transmit and receive. this interface operates at either 10 mbps or 100 mbps. the speed is set automatically, once the operating conditions of the network link have been determined. refer to mii operation on page 18 for additional details. configuration management interface the LXT972 provides both an mdio interface and a hardware control interface for device configuration and management. mdio management interface the LXT972 supports the ieee 802.3 mii management interface also known as the management data input/output (mdio) interface. this interface allows upper-layer devices to monitor and control the state of the LXT972. the mdio interface consists of a physical connection, a specific protocol that runs across the connection, and an internal set of addressable registers. some registers are required and their functions are defined by the ieee 802.3 standard. the LXT972 also supports additional registers for expanded functionality. the LXT972 supports multiple internal registers, each of which is 16 bits wide. specific register bits are referenced using an x.y notation, where x is the register number (0-31) and y is the bit number (0-15). the physical interface consists of a data line (mdio) and clock line (mdc). operation of this interface is controlled by the mddis input pin. when mddis is high, the mdio read and write operations are disabled and the hardware control interface provides primary configuration control. when mddis is low, the mdio port is enabled for both read and write operations and the hardware control interface is not used. mdio addressing the protocol allows one controller to communicate between two LXT972 chips. pin addr0 is set high or low to determine the chip address. mdio frame structure the physical interface consists of a data line (mdio) and clock line (mdc). the frame structure is shown in figures 2 and 3 (read and write). mdio interface timing is shown in table 32 on page 46 . figure 2: management interface read frame structure mdc mdio (read) 32 "1"s 0110 preamble st op code phy address turn around z0 a4 a3 a0 r4 r3 r0 register address d15 d14 d1 data write read d15 d14 d1 d0 idle high z figure 3: management interface write frame structure mdc mdio (write) 32 "1"s 0101 preamble st op code phy address turn around 1 0 a4 a3 a0 r4 r3 r0 re g ister address d15 d14 d1 d0 data idle idle write
LXT972 functional description 13 mii interrupts the LXT972 provides a single interrupt pin (mdint ). interrupt logic is shown in figure 4 . the LXT972 also provides two dedicated interrupt registers. register 18 provides interrupt enable and mask functions and reg- ister 19 provides interrupt status. setting bit 18.1 = 1, enables the device to request interrupt via the mdint pin. an active low on this pin indicates a status change on the LXT972. interrupts may be caused by four conditions: ? auto-negotiation complete ? speed status change ? duplex status change ? link status change hardware control interface the LXT972 provides a hardware control interface for applications where the mdio is not desired. the hardware control interface uses the three led driver pins to set device configuration. refer to the hardware configuration settings section on page 16 for additional details. figure 4: interrupt logic force interrupt interrupt enable event x mask reg event x status reg interrupt pin . . . and or nand per event 1. interrupt (event) status register is cleared on read. (mdint )
LXT972 3.3v dual-speed fast ethernet transceiver 14 operating requirements power requirements the LXT972 requires three power supply inputs (vccd, vcca, and vccio). the digital and analog circuits require 3.3v supplies (vccd and vcca). these inputs may be supplied from a single source. each supply input must be decoupled to ground. an additional supply may be used for the mii (vccio). the supply may be either +2.5v or +3.3v. also, the inputs on the mii interface are tolerant to 5v signals from the controller on the other side of the mii interface. refer to table 19 on page 37 for mii i/o characteristics. as a matter of good practice, these supplies should be as clean as possible. clock requirements external crystal/oscillator the LXT972 requires a reference clock input. it may be provided by either of two methods: by connecting a crystal across the oscillator pins (xi and xo), or by connecting an external clock source to pin xi. when a clock is supplied to xi, xo is left open. a crystal is typically used in nic applications. an external 25 mhz clock source, rather than a crystal, is frequently used in switch applications. refer to preliminary test specifications, table 20 on page 37 , for clock timing requirements. mdio clock the mii management channel (mdio) also requires an external clock. the managed data clock (mdc) speed is a maximum of 8 mhz. refer to table 32 on page 46 for details. initialization when the LXT972 is first powered on, reset, or encounters a link failure state, it checks the mdio register configuration bits to determine the line speed and operating conditions to use for the network link. the configuration bits may be set by the hardware control or mdio interface as shown in figure 5 . mdio control mode in the mdio control mode, the LXT972 reads the hardware control interface pins to set the initial (default) values of the mdio registers. once the initial values are set, bit control reverts to the mdio interface. hardware control mode in the hardware control mode, LXT972 disables direct write operations to the mdio registers via the mdio interface. on power-up or hardware reset the LXT972 reads the hardware control interface pins and sets the mdio registers accordingly. the following modes are available using either hardware control or mdio control: ? force network link operation to: 100tx, full-duplex. 100tx, half-duplex. 10base-t, full-duplex. 10base-t, half-duplex. ? allow auto-negotiation / parallel-detection. when the network link is forced to a specific configuration, the LXT972 immediately begins operating the network interface as commanded. when auto-negotiation is enabled, the LXT972 begins the auto-negotiation / parallel- detection operation. figure 5: initialization sequence mddis volta g e level? hi g h low mdio control mode hardware control mode disable mdio read and write operations reset mdio re g isters to values read at h/w control interface at last hardware reset mdio controlled operation (mdio writes enabled) power-up or reset initialize mdio re g isters read h/w control interface software reset? yes no
LXT972 functional description 15 reduced power modes the LXT972 offers two power-down modes. hardware power down the hardware power-down mode is controlled by the pwrdwn pin. when pwrdwn is high, the follow- ing conditions are true: ? the LXT972 network port and clock are shut down. ? all outputs are tri-stated. ? all weak pad pull-up and pull-down resistors are disabled. ? the mdio registers are not accessible. software power down software power-down control is provided by bit 0.11 in the control register (refer to table 37 on page 51 ). during soft power-down, the following conditions are true: ? the network port is shut down. ? the mdio registers remain accessible. reset the LXT972 provides both hardware and software resets. configuration control of auto-negotiation, speed and duplex mode selection is handled differently for each. during a hardware reset, auto-negotiation and speed are read in from pins (refer to table 8 on page 16 for pin settings and to table 37 on page 51 for register bit definitions). during a software reset (0.15 = 1), these bit settings are not re-read from the pins. they revert back to the values that were read in during the last hardware reset. therefore, any changes to pin values made since the last hardware reset will not be detected during a software reset. during a hardware reset, register information is unavailable for 1 ms after de-assertion of the reset. during a software reset (0.15 = 1) the registers are available for reading. the reset bit should be polled to see when the part has completed reset (0.15 = 0).
LXT972 3.3v dual-speed fast ethernet transceiver 16 hardware configuration settings the LXT972 provides a hardware option to set the initial device configuration. the hardware option uses the three led driver pins. this provides three control bits, as listed in table 8 . the led drivers can operate as either open- drain or open-source circuits as shown in figure 6 . . figure 6: hardware configuration settings configuration bit = 1 configuration bit = 0 led/cfg pin led/cfg pin 1. the led/cfg pins will automatically adjust their polarity upon power-up or reset. 3.3v table 8: hardware configuration settings desired mode led/cfg n pin settings 1 resulting register bit values control register auto-neg advertisement auto-neg speed (mbps) duplex 1 2 3 autoneg 0.12 speed 0.13 fd 0.8 100fd 4.8 100tx 4.7 10fd 4.6 10t 4.5 disabled 10 half low low low 0 0 0 n/a auto-negotiation advertisement full low low high 1 100 half low high low 1 0 full low high high 1 enabled 100 only half high low low 1 1 0 0 1 0 0 full high low high 1 1 1 0 0 10/100 half only high high low 0 0 1 0 1 full or half high high high 1 1 1 1 1 1. refer to table 7 on page 9 for led/cfg pin assignments.
LXT972 functional description 17 establishing link see figure 7 for an overview of link establishment. auto-negotiation if not configured for forced operation, the LXT972 attempts to auto-negotiate with its link partner by sending fast link pulse (flp) bursts. each burst consists of up to 33 link pulses spaced 62.5 m s apart. odd link pulses (clock pulses) are always present. even link pulses (data pulses) may be present or absent to indicate a 1 or a 0. each flp burst exchanges 16 bits of data, which are referred to as a link code word. all devices that support auto- negotiation must implement the base page defined by ieee 802.3 (registers 4 and 5). LXT972 also supports the optional next page function as described in tables 44 and 45 (registers 7 and 8). base page exchange by exchanging base pages, the LXT972 and its link partner communicate their capabilities to each other. both sides must receive at least three identical base pages for negotiation to continue. each side identifies the highest common capabilities that both sides support and configures itself accordingly. next page exchange additional information, above that required by base page exchange, is also sent via next pages. the LXT972 fully supports the ieee 802.3ab method of negotiation via next page exchange. controlling auto-negotiation when auto-negotiation is controlled by software, the following steps are recommended: ? after power-up, power-down, or reset, the power-down recovery time, as specified in table 34 on page 47 , must be exhausted before proceeding. ? set the auto-negotiation advertisement register bits. ? enable auto-negotiation (set mdio bit 0.12 = 1). parallel detection for the parallel detection feature of auto-negotiation, the LXT972 also monitors for 10base-t normal link pulses (nlp) and 100base-tx idle symbols. if either is detected, the device automatically reverts to the corresponding operating mode. parallel detection allows the LXT972 to communicate with devices that do not support auto-negotiation. figure 7: link establishment overview check value 0.12 start done enable auto-neg/parallel detection go to forced settings attempt auto- negotiation listen for 10t link pulses listen for 100tx idle symbols link up? no yes power-up, reset, or link failure disable auto-negotiation 0.12 = 0 0.12 = 1
LXT972 3.3v dual-speed fast ethernet transceiver 18 mii operation the LXT972 device implements the media independent interface (mii) as defined in the ieee 802.3 standard. separate channels are provided for transmitting data from the mac to the LXT972 (txd), and for passing data received from the line (rxd) to the mac. each channel has its own clock, data bus, and control signals. nine signals are used to pass received data to the mac: rxd<3:0>, rx_clk, rx_dv, rx_er, col, and crs. seven signals are used to transmit data from the mac: txd<3:0>, tx_clk, tx_en, and tx_er. the LXT972 supplies both clock signals as well as separate outputs for carrier sense and collision. data transmission across the mii is normally implemented in 4-bit-wide nibbles. mii clocks the LXT972 is the master clock source for data transmission and supplies both mii clocks (rx_clk and tx_clk). it automatically sets the clock speeds to match link conditions. when the link is operating at 100 mbps, the clocks are set to 25 mhz. when the link is operating at 10 mbps, the clocks are set to 2.5 mhz. figures 8 through 10 show the clock cycles for each mode. the transmit data and control signals must always be synchronized to tx_clk by the mac. the LXT972 samples these signals on the rising edge of tx_clk. transmit enable the mac must assert tx_en the same time as the first nibble of preamble, and de-assert tx_en after the last bit of the packet. receive data valid the LXT972 asserts rx_dv when it receives a valid packet. timing changes depend on line operating speed: ? for 100tx links, rx_dv is asserted from the first nibble of preamble to the last nibble of the data packet. ? for 10bt links, the entire preamble is truncated. rx_dv is asserted with the first nibble of the start of frame delimiter (sfd) 5d and remains asserted until the end of the packet. carrier sense carrier sense (crs) is an asynchronous output. it is always generated when a packet is received from the line and in half-duplex when a packet is transmitted. carrier sense is not generated when a packet is transmitted and in full-duplex mode. table 9 summarizes the conditions for assertion of carrier sense, collision, and data loopback signals. error signals when LXT972 is in 100 mbps mode and receives an invalid symbol from the network, it asserts rx_er and drives 1110 on the rxd pins. when the mac asserts tx_er, the LXT972 will drive h symbols out on the tpop/n pins. collision the LXT972 asserts its collision signal, asynchronously to any clock, whenever the line state is half-duplex and the transmitter and receiver are active at the same time. table 9 summarizes the conditions for assertion of carrier sense, collision, and data loopback signals.
LXT972 functional description 19 figure 8: 10base-t clocking rx_clk (sourced by LXT972) 2.5 mhz during auto-negotiation and 10base-t data & idle tx_clk (sourced by LXT972) 2.5 mhz during auto-negotiation and 10base-t data & idle constant 25 mhz xi figure 9: 100base-x clocking rx_clk (sourced by LXT972) 2.5 mhz during auto-negotiation tx_clk (sourced by LXT972) constant 25 mhz xi 25 mhz once 100base-x link established 2.5 mhz during auto-negotiation 25 mhz once 100base-x link established
LXT972 3.3v dual-speed fast ethernet transceiver 20 loopback the LXT972 provides two loopback functions, operational and test (see table 9 ). loopback paths are shown in figure 11 . operational loopback operational loopback is provided for 10 mbps half- duplex links when bit 16.8 = 0. data transmitted by the mac (txdata) will be looped back on the receive side of the mii (rxdata). operational loopback is not provided for 100 mbps links, full-duplex links, or when 16.8 = 1. test loopback a test loopback function is provided for diagnostic testing of the LXT972. during test loopback, the twisted-pair interface is disabled. data transmitted by the mac is internally looped back by the LXT972 and returned to the mac. test loopback is available for both 100tx and 10t operation. test loopback is enabled by setting bits as follows: ? 0.14 = 1 ? 0.8 = 1 (full-duplex) ? 0.12 = 0 (disable auto-negotiation). figure 10: link down clock transition any clock 2.5mhz clock clock transition time will not exceed 2x the link down condition/auto negotiate enabled rx_clk tx_clk nominal clock period: (10 mbps = 2.5 mhz 100 mbps = 25 mhz) figure 11: loopback paths 10t loopback digital block mii tx driver 100x loopback analog block LXT972 table 9: carrier sense, loopback, and collision conditions speed duplex condition carrier sense test 1 loopback operational loopback collision 100 mbps full-duplex receive only yes no none half-duplex transmit or receive no no transmit and receive 10 mbps full-duplex receive only yes no none half-duplex, 16.8 = 0 transmit or receive yes yes transmit and receive half-duplex, 16.8 = 1 transmit or receive no no transmit and receive 1. test loopback is enabled when 0.14 = 1
LXT972 functional description 21 100 mbps operation 100base-x network operations during 100base-x operation, the LXT972 transmits and receives 5-bit symbols across the network link. figure 12 shows the structure of a standard frame packet. when the mac is not actively transmitting data, the LXT972 sends out idle symbols on the line. in 100tx mode, the LXT972 scrambles and transmits the data to the network using mlt-3 line code ( figure 13 on page 22 ). mlt-3 signals received from the network are descrambled, decoded, and sent across the mii to the mac. . figure 12: 100base-x frame format p0 p1 p6 sfd 64-bit preamble (8 octets) start-of-frame delimiter (sfd) da da sa sa destination and source address (6 octets each) l1 l2 packet length (2 octets) d0 d1 dn data field (pad to minimum packet size) frame check field (4 octets) crc i0 interframe gap / idle code (> 12 octets) replaced by /t/r/ code-groups end-of-stream delimiter (esd) ifg replaced by /j/k/ code-groups start-of-stream delimiter (ssd)
LXT972 3.3v dual-speed fast ethernet transceiver 22 figure 13: 100base-tx data path s0 s1 s2 s3 s4 parallel to serial serial to parallel mlt3 0 +1 -1 00 transition = 1. no transition = 0. all transitions must follow pattern: 0, +1, 0, -1, 0, +1... scrambler bypass data flow s0 s1 s2 s3 s4 standard data flow d0 d1 d2 d3 parallel to serial serial to parallel d0 d1 d2 d3 4b/5b s0 s1 s2 s3 s4 mlt3 0 +1 -1 00 transition = 1. no transition = 0. all transitions must follow pattern: 0, +1, 0, -1, 0, +1... scramble de- scramble
LXT972 functional description 23 as shown in figure 12 on page 21 , the mac starts each transmission with a preamble pattern. as soon as the LXT972 detects the start of preamble, it transmits a start- of-stream delimiter (ssd, symbols j and k) to the network. it then encodes and transmits the rest of the packet, including the balance of the preamble, the sfd, packet data, and crc. once the packet ends, the LXT972 transmits the end-of stream-delimiter (esd, symbols t and r) and then returns to transmitting idle symbols. 4b/5b coding is shown in table 10 on page 26 . figure 14 shows normal reception with no errors. when the LXT972 receives invalid symbols from the line, it asserts rx_er as shown in figure 15 . figure 14: 100base-tx reception with no errors rx_clk rx_dv rxd<3:0> rx_er preamble sfd sfd da da da da crc crc crc crc figure 15: 100base-tx reception with invalid symbol rx_clk rx_dv rxd<3:0> rx_er preamble sfd sfd da da xx xx xx xx xx xx xx xx xx xx
LXT972 3.3v dual-speed fast ethernet transceiver 24 collision indication figure 16 shows normal transmission. upon detection of a collision, the col output is asserted and remains asserted for the duration of the collision as shown in figure 17 . figure 16: 100base-tx transmission with no errors da da da da da da da da da tx_clk tx_en txd<3:0> crs col pr ea mb le figure 17: 100base-tx transmission with collision jam tx_clk tx_en txd<3:0> crs col pr ea mb le jam jam jam
LXT972 functional description 25 100base-x protocol sublayer operations with respect to the 7-layer communications model, the LXT972 is a physical layer 1 (phy) device. the LXT972 implements the physical coding sublayer (pcs), physical medium attachment (pma), and physical medium dependent (pmd) sublayers of the reference model defined by the ieee 802.3u standard. the following paragraphs discuss LXT972 operation from the reference model point of view. pcs sublayer the physical coding sublayer (pcs) provides the mii interface, as well as the 4b/5b encoding/ decoding function. for 100tx operation, the pcs layer provides idle symbols to the pmd-layer line driver as long as tx_en is de-asserted. preamble handling when the mac asserts tx_en, the pcs substitutes a /j/k symbol pair, also known as the start-of-stream delimiter (ssd), for the first two nibbles received across the mii. the pcs layer continues to encode the remaining mii data, following the coding in table 10 on page 26 , until tx_en is de-asserted. it then returns to supplying idle symbols to the line driver. in the receive direction, the pcs layer performs the opposite function, substituting two preamble nibbles for the ssd. dribble bits the LXT972 handles dribbles bits in all modes. if between 1-4 dribble bits are received, the nibble will be passed across the mii, padded with 1s if necessary. if between 5-7 dribble bits are received, the second nibble will not be sent onto the mii bus. figure 18: protocol sublayers encoder/decoder serializer/de-serializer link/carrier detect pcs sublayer pma sublayer mii interface LXT972 100base-tx scrambler/ de-scrambler pmd sublayer
LXT972 3.3v dual-speed fast ethernet transceiver 26 table 10: 4b/5b coding code type 4b code 3 2 1 0 name 5b code 4 3 2 1 0 interpretation 0 0 0 0 0 1 1 1 1 0 data 0 0 0 0 1 1 0 1 0 0 1 data 1 0 0 1 0 2 1 0 1 0 0 data 2 0 0 1 1 3 1 0 1 0 1 data 3 0 1 0 0 4 0 1 0 1 0 data 4 0 1 0 1 5 0 1 0 1 1 data 5 0 1 1 0 6 0 1 1 1 0 data 6 data 0 1 1 1 7 0 1 1 1 1 data 7 1 0 0 0 8 1 0 0 1 0 data 8 1 0 0 1 9 1 0 0 1 1 data 9 1 0 1 0 a 1 0 1 1 0 data a 1 0 1 1 b 1 0 1 1 1 data b 1 1 0 0 c 1 1 0 1 0 data c 1 1 0 1 d 1 1 0 1 1 data d 1 1 1 0 e 1 1 1 0 0 data e 1 1 1 1 f 1 1 1 0 1 data f idle undefined i 1 1 1 1 11 idle. used as inter-stream fill code 0 1 0 1 j 2 1 1 0 0 0 start-of-stream delimiter (ssd), part 1 of 2 control 0 1 0 1 k 2 1 0 0 0 1 start-of-stream delimiter (ssd), part 2 of 2 undefined t 3 0 1 1 0 1 end-of-stream delimiter (esd), part 1 of 2 undefined r 3 0 0 1 1 1 end-of-stream delimiter (esd), part 2 of 2 undefined h 4 0 0 1 0 0 transmit error. used to force signaling errors undefined invalid 0 0 0 0 0 invalid undefined invalid 0 0 0 0 1 invalid undefined invalid 0 0 0 1 0 invalid invalid undefined invalid 0 0 0 1 1 invalid undefined invalid 0 0 1 0 1 invalid undefined invalid 0 0 1 1 0 invalid undefined invalid 0 1 0 0 0 invalid undefined invalid 0 1 1 0 0 invalid undefined invalid 1 0 0 0 0 invalid undefined invalid 1 1 0 0 1 invalid 1. the /i/ (idle) code group is sent continuously between frames. 2. the /j/ and /k/ (ssd) code groups are always sent in pairs; /k/ follows /j/. 3. the /t/ and /r/ (esd) code groups are always sent in pairs; /r/ follows /t/. 4. an /h/ (error) code group is used to signal an error condition.
LXT972 functional description 27 pma sublayer link in 100 mbps mode, the LXT972 establishes a link whenever the scrambler becomes locked and remains locked for approximately 50 ms. whenever the scrambler loses lock (receiving less than 12 consecutive idle symbols during a 2 ms window), the link will be taken down. this provides a very robust link, essentially filtering out any small noise hits that may otherwise disrupt the link. furthermore 100m idle patterns will not bring up a 10m link. the LXT972 reports link failure via the mii status bits (1.2 and 17.10) and interrupt functions. if auto- negotiation is enabled, link failure causes the LXT972 to re-negotiate. link failure override the LXT972 will normally transmit data packets only if it detects the link is up. setting bit 16.14 = 1 overrides this function, allowing the LXT972 to transmit data packets even when the link is down. this feature is provided as a diagnostic tool. note that auto-negotiation must be disabled to transmit data packets in the absence of link. if auto-negotiation is enabled, the LXT972 will automatically transmit flp bursts if the link is down. carrier sense for 100tx links, a start-of-stream delimiter (ssd) or /j/k symbol pair causes assertion of carrier sense (crs). an end-of-stream delimiter (esd) or /t/r symbol pair causes de-assertion of crs. the pma layer will also de-assert crs if idle symbols are received without /t/r; however, in this case rx_er will be asserted for one clock cycle when crs is de- asserted. usage of crs for interframe gap (ifg) timing is not recommended for the following reasons: ? de-assertion time for crs is slightly longer than assertion time. this causes ifg intervals to appear somewhat shorter to the mac than it actually is on the wire. ? crs de-assertion is not aligned with tx_en de- assertion on transmit loopbacks in half-duplex mode. receive data valid the LXT972 asserts rx_dv to indicate that the received data maps to valid symbols. however, rxd outputs zeros until the received data is decoded and available for transfer to the controller. twisted-pair pmd sublayer the twisted-pair physical medium dependent (pmd) layer provides the signal scrambling and descrambling, line coding and decoding (mlt-3 for 100tx, manchester for 10t), as well as receiving, polarity correction, and baseline wander correction functions. scrambler/descrambler the purpose of the scrambler is to spread the signal power spectrum and further reduce emi using an 11-bit, data-independent polynomial. the receiver automatically decodes the polynomial whenever idle symbols are received. scrambler seeding. once the transmit data (or idle symbols) are properly encoded, they are scrambled to further reduce emi and to spread the power spectrum using an 11-bit scrambler seed. five seed bits are determined by the phy address, and the remaining bits are hard coded in the design. scrambler bypass. the scrambler/descrambler can be bypassed by setting bit 16.12 = 1. scrambler bypass is provided for diagnostic and test support. baseline wander correction the LXT972 provides a baseline wander correction function which makes the device robust under all network operating conditions. the mlt3 coding scheme used in 100base-tx is by definition unbalanced. this means that the average value of the signal voltage can wander significantly over short time intervals (tenths of seconds). this wander can cause receiver errors at long-line lengths (100 meters) in less robust designs. exact characteristics of the wander are completely data dependent. the LXT972 baseline wander correction characteristics allow the device to recover error-free data while receiving worst-case killer packets over all cable lengths. polarity correction the 100base-tx descrambler automatically detects and corrects for the condition where the receive signal at tpip and tpin is inverted. programmable slew rate control the LXT972 device supports a slew rate mechanism whereby one of four pre-selected slew rates can be used. this allows the designer to optimize the output waveform to match the characteristics of the magnetics. the slew rate is determined by the txslew pins as shown in table 4 on page 8 .
LXT972 3.3v dual-speed fast ethernet transceiver 28 10 mbps operation the LXT972 operates as a standard 10base-t transceiver. the LXT972 supports all the standard 10 mbps functions. during 10base-t (10t) operation, the LXT972 transmits and receives manchester-encoded data across the network link. when the mac is not actively transmitting data, the LXT972 drives link pulses onto the line. in 10t mode, the polynomial scrambler/descrambler is inactive. manchester-encoded signals received from the network are decoded by the LXT972 and sent across the mii to the mac. 10t preamble handling the LXT972 offers two options for preamble handling, selected by bit 16.5. in 10t mode when 16.5 = 0, the LXT972 strips the entire preamble off of received packets. crs is asserted coincident with sfd. rx_dv is held low for the duration of the preamble. when rx_dv is asserted, the very first two nibbles driven by the LXT972 are the sfd 5d hex followed by the body of the packet. in 10t mode with 16.5 = 1, the LXT972 passes the preamble through the mii and asserts rx_dv and crs simultaneously. in 10t loopback, the LXT972 loops back whatever the mac transmits to it, including the preamble. 10t carrier sense for 10t links, crs assertion is based on reception of valid preamble, and de-assertion on reception of an end-of-frame (eof) marker. bit 16.7 allows crs de-assertion to be synchronized with rx_dv de-assertion. refer to table 46 on page 58 . 10t dribble bits the LXT972 device handles dribbles bits in all modes. if between 1-4 dribble bits are received, the nibble will be passed across the mii, padded with 1s if necessary. if between 5-7 dribble bits are received, the second nibble will not be sent onto the mii bus. 10t link integrity test in 10t mode, the LXT972 always transmits link pulses. when the link integrity test function is enabled (the normal configuration), it monitors the connection for link pulses. once link pulses are detected, data transmission will be enabled and will remain enabled as long as either the link pulses or data transmission continue. if the link pulses stop, the data transmission will be disabled. if the link integrity test function is disabled, the LXT972 will transmit to the connection regardless of detected link pulses. the link integrity test function can be disabled by setting bit 16.14 = 1. link failure link failure occurs if link integrity test is enabled and link pulses or packets stop being received. if this condition occurs, the LXT972 returns to the auto- negotiation phase if auto-negotiation is enabled. if the link integrity test function is disabled by setting 16.14 = 1 in the configuration register, the LXT972 will transmit packets, regardless of link status. 10t sqe (heartbeat) by default, the signal quality error (sqe) or heartbeat function is disabled on the LXT972. to enable this function, set bit 16.9 = 1. when this function is enabled, the LXT972 will assert its col output for 5-15 bt after each packet. see figure 28 on page 44 for sqe timing parameters. 10t jabber if a transmission exceeds the jabber timer, the LXT972 will disable the transmit and loopback functions. see figure 27 on page 44 for jabber timing parameters. the LXT972 automatically exits jabber mode after the unjabber time has expired. this function can be disabled by setting bit 16.10 = 1. 10t polarity correction the LXT972 automatically detects and corrects for the condition where the receive signal (tpip/n) is inverted. reversed polarity is detected if eight inverted link pulses, or four inverted end-of-frame (eof) markers, are received consecutively. if link pulses or data are not received by the maximum receive time-out period (96-128 ms), the polarity state is reset to a non-inverted state.
LXT972 functional description 29 monitoring operations monitoring auto-negotiation auto-negotiation can be monitored as follows: ? bit 17.7 is set to 1 once the auto-negotiation process is completed. ? bits 1.2 and 17.10 are set to 1 once the link is established. ? bits 17.14 and 17.9 can be used to determine the link operating conditions (speed and duplex). monitoring next page exchange the LXT972 offers an alternate next page mode to simplify the next page exchange process. normally, bit 6.1 (page received) remains set until read. when alternate next page mode is enabled (16.1 = 1), bit 6.1 is automatically cleared whenever a new negotiation process takes place. this prevents the user from reading an old value in 6.1 and assuming that registers 5 and 8 (partner ability) contain valid information. additionally, the LXT972 uses bit 6.5 to indicate when the current received page is the base page. this information is useful for recognizing when next pages must be resent due to a new negotiation process starting. bits 6.1 and 6.5 are cleared when read. led functions the LXT972 incorporates three direct led drivers. on power up all the drivers are asserted for approximately 1 second after reset de-asserts. each led driver can be programmed using the led configuration register (refer to table 50 on page 62 ) to indicate one the following conditions: ? operating speed ? transmit activity ? receive activity ? collision condition ? link status ? duplex mode the led drivers can also be programmed to display vari- ous combined status conditions. for example, setting bits 20.15:12 = 1101 produces the following combination of link and activity indications: ? if link is down led is off. ? if link is up led is on. ? if link is up and activity is detected, the led will blink at the stretch interval selected by bits 20.3:2 and will continue to blink as long as activity is present.
LXT972 3.3v dual-speed fast ethernet transceiver 30 the led driver pins also provide initial configuration settings. the led pins are sensitive to polarity and will automatically pull up or pull down to configure for either open drain or open source circuits (10 ma max current rating) as required by the hardware configuration. refer to the discussion of hardware configuration settings on page 16 for details. led pulse stretching the led configuration register also provides optional led pulse stretching to 30, 60, or 100 ms. if during this pulse stretch period, the event occurs again, the pulse stretch time will be further extended. when an event such as receiving a packet occurs it will be edge detected and it will start the stretch timer. the led driver will remain asserted until the stretch timer expires. if another event occurs before the stretch timer expires then the stretch timer will be reset and the stretch time will be extended. when a long event (such as duplex status) occurs it will be edge detected and it will start the stretch timer. when the stretch timer expires the edge detector will be reset so that a long event will cause another pulse to be generated from the edge detector which will reset the stretch timer and cause the led driver to remain asserted. figure 19 shows how the stretch operation functions. figure 19: led pulse stretching event led note: the direct drive led outputs in this diagram are shown as active low. stretch stretch stretch
LXT972 functional description 31 boundary scan (jtag1149.1) functions LXT972 includes a ieee 1149.1 boundary scan test port for board level testing. all digital input, output, and input/ output pins are accessible. the bsdl file is available by contacting your local sales office (see the back page) or by accessing the level one website (www.level1.com) . boundary scan interface this interface consists of five pins (tms, tdi, tdo, trst , and tck). it includes a state machine, data register array, and instruction register. the tms and tdi pins are internally pulled up. tck is internally pulled down. tdo does not have an internal pull-up or pull-down. state machine the tap controller is a 16 state machine driven by the tck and tms pins. upon reset the test_logic_reset state is entered. the state machine is also reset when tms and tdi are high for five tck periods. instruction register after the state machine resets, the idcode instruction is always invoked. the decode logic ensures the correct data flow to the data registers according to the current instruction. valid instructions are listed in table 12 . boundary scan register (bsr) each boundary scan register (bsr) cell has two stages. a flip-flop and a latch are used for the serial shift stage and the parallel output stage. there are four modes of operation as listed in table 11 . table 11: bsr mode of operation mode description 1capture 2shift 3 update 4 system function table 12: supported jtag instructions name code description mode data register extest 0000 external test test bsr idcode 0001 id code inspection normal id reg sample 0010 sample boundary normal bsr tribyp 0011 force float normal bypass setbyp 0100 control boundary to 1/0 test bypass bypass 1111 bypass scan normal bypass table 13: device id register 31:28 27:12 11:8 7:1 0 version part id (hex) jedec continuation characters jedec id 1 reserved 0001 03cb 1110 111 1110 1 1. the jedec is is an 8-bit identifier. the msb is for parity and is ignored. level ones jedec id is fe (1111 1110) which becom es 111 1110
LXT972 3.3v dual-speed fast ethernet transceiver 32 application information magnetics information the LXT972 requires a 1:1 ratio for both the receive and transmit transformers. the transformer isolation voltage should be rated at 2 kv to protect the circuitry from static voltages across the connectors and cables. refer to table 14 for transformer requirements. a cross-reference list of magnetic manufacturers and part numbers is available in application note 073, magnetic manufacturers, which can be found on the level one web site (www.level1.com). before committing to a specific component, designers should contact the manufacturer for current product specifications, and validate the magnetics for the specific application. typical twisted-pair interface table 15 provides a comparison of the rj-45 connections for nic and switch applications in a typical twisted-pair interface setting. figure 20 on page 33 shows a typical twisted-pair interface with the rj-45 connections crossed over for a switch configuration. figure 21 on page 34 provides a typical twisted-pair interface with the rj-45 connections configured for a nic application. table 14: magnetics requirements parameter min nom max units test condition rx turns ratio C 1 : 1 C C tx turns ratio C 1 : 1 C C insertion loss 0.0 0.6 1.1 db primary inductance 350 C C m h transformer isolation C 1.5 C kv differential to common mode rejection 40 C C db .1 to 60 mhz 35 C C db 60 to 100 mhz return loss -16 C C db 30 mhz -10 C C db 80 mhz table 15: rj-45 pin comparison of nic and switch twisted-pair interfaces symbol rj-45 switch nic tpip 1 3 tpin 2 6 tpop 3 1 tpon 6 2
LXT972 application information 33 figure 20: typical twisted-pair interface - switch tpip tpin rj-45 * = 0.001 m f / 2.0 kv to twisted-pair network 3 6 1 2 1:1 LXT972 50 w 50 w 50 w 50 w 50 w 50 w 4 5 8 7 1:1 1 tpop tpon vcca gnd 0.1 m f .01 m f 2 270 pf 5% 270 pf 5% 0.01 m f 50 w 1% 50 w 1% ** 3 4 0.1 m f 1. center-tap current may be supplied from 3.3v vcca as shown. additional power savings may be realized by supplying the center-tap from a 2.5v current source. a separate ferrite bead (rated at 50 ma) should be used to supply center-tap current. 2. the 100 w transmit load termination resistor typically required is integrated in the LXT972. 3. magnetics without a receive pair center-tap do not require a 2 kv termination. 4. rj-45 connections shown are for a standard switch application. for a standard nic rj-45 setup, see figure 21 .
LXT972 3.3v dual-speed fast ethernet transceiver 34 figure 21: typical twisted-pair interface - nic tpip tpin * = 0.001 m f / 2.0 kv to twisted-pair network 1:1 LXT972 1:1 1 tpop tpon vcca gnd 0.1 m f .01 m f 2 270 pf 5% 270 pf 5% 0.01 m f 50 w 1% 50 w 1% ** 3 6 3 8 7 5 4 1 2 50 w 50 w 50 w rj-45 50 w 50 w 50 w 4 0.1 m f 1. center-tap current may be supplied from 3.3v vcca as shown. additional power savings may be realized by supplying the center-tap from a 2.5v current source. a separate ferrite bead (rated at 50 ma) should be used to supply center-tap current. 2. the 100 w transmit load termination resistor typically required is integrated in the LXT972. 3. magnetics without a receive pair center-tap do not require a 2 kv termination. 4. rj-45 connections shown are for a standard nic. tx/rx crossover may be required for repeater & switch applications..
LXT972 application information 35 figure 22: typical mii interface mac tx_en tx_er txd<3:0> tx_clk rx_dv rx_er rxd<3:0> crs col LXT972 x rj-45 f m r rx_clk
LXT972 3.3v dual-speed fast ethernet transceiver 36 preliminary test specifications note tables 16 through 34 and figures 23 through 34 represent the target specifications of the LXT972. these specifications are guaranteed by test except where noted by design. minimum and maximum values listed in tables 18 through 34 apply over the recommended operating conditions specified in table 17 . electrical parameters table 16: absolute maximum ratings parameter sym min max units supply voltage v cc -0.3 4.0 v operating temperature t opa 0+70 oc storage temperature t st -65 +150 oc caution exceeding these values may cause permanent damage. functional operation under these conditions is not implied. exposure to maximum rating conditions for extended periods may affect device reliability. table 17: operating conditions parameter sym min typ 1 max units recommended operating temperature LXT972_c (commercial) t opa 0C70oc recommended supply voltage 2 analog & digital v cca , v ccd 3.14 3.3 3.45 v i/o v ccio 2.35 C 3.45 v v cc current 100base-tx i cc CC110ma 10base-t i cc CC82ma power down i cc CC 1ma auto-negotiation i cc CC110ma 1. typical values are at 25 c and are for design aid only; not guaranteed and not subject to production testing. 2. voltages with respect to ground unless otherwise specified.
LXT972 preliminary test specifications 37 table 18: digital i/o characteristics 1 parameter symbol min typ 2 max units test conditions input low voltage v il CC0.8v C input high voltage v ih 2.0 C C v C input current i i -10 C 10 m a 0.0 < v i < v cc output low voltage v ol CC0.4vi ol = 4 ma output high voltage v oh 2.4 C C v i oh = -4 ma 1. applies to all pins except mii , led and xi/xo pins. refer to table 19 for mii i/o characteristics, table 20 for xi/xo and table 21 for led characteristics. 2. typical values are at 25 c and are for design aid only; not guaranteed and not subject to production testing. table 19: digital i/o characteristics - mii pins parameter symbol min typ 1 max units test conditions input low voltage v il CC0.8v C input high voltage v ih 2.0 C C v C input current i i -10 C 10 m a 0.0 < v i < vccio output low voltage v ol CC0.4vi ol = 4 ma output high voltage v oh 2.2 C C v i oh = -4 ma, vccio = 3.3v v oh 2.0 C C v i oh = -4 ma, vccio = 2.5v driver output resistance (line driver output enabled) r o 2 C 100 C w vccio = 2.5v r o 2 C 100 C w vccio = 3.3v 1. typical values are at 25 c and are for design aid only; not guaranteed and not subject to production testing. 2. parameter is guaranteed by design; not subject to production testing. table 20: i/o characteristics - refclk/xi and xo pins parameter sym min typ 1 max units test conditions input low voltage v il CC0.8v input high voltage v ih 2.0 C C v input clock frequency tolerance 2 d f CC 100 ppm input clock duty cycle 2 t dc 40 C 60 % input capacitance c in C3.0 C pf 1. typical values are at 25 c and are for design aid only; not guaranteed and not subject to production testing. 2. parameter is guaranteed by design; not subject to production testing.
LXT972 3.3v dual-speed fast ethernet transceiver 38 table 21: i/o characteristics - led/cfg pins parameter sym min typ max units test conditions output low voltage v ol CC0.4vi ol = 10 ma output high voltage v oh 2.4 C C v i oh = -10 ma input current i i -10 C 10 m a0 < v i < vccio table 22: 100base-tx transceiver characteristics parameter sym min typ 1 max units test conditions peak differential output voltage v p 0.95 C 1.05 v note 2 signal amplitude symmetry vss 98 C 102 % note 2 signal rise/fall time t rf 3.0 C 5.0 ns note 2 rise/fall time symmetry t rfs C C 0.5 ns note 2 duty cycle distortion d cd 35 50 65 % offset from 16ns pulse width at 50% of pulse peak overshoot/undershoot v os CC 5 % C jitter (measured differentially) C C C 1.4 ns C 1. typical values are at 25 c and are for design aid only; not guaranteed and not subject to production testing. 2. measured at the line side of the transformer, line replaced by 100 w (+/-1%) resistor. table 23: 10base-t transceiver characteristics parameter sym min typ max units test conditions transmitter peak differential output voltage v op 2.2 2.5 2.8 v with transformer, line replaced by 100 w resistor transition timing jitter added by the mau and pls sections - 0 2 11 ns after line model spec- ified by ieee 802.3 for 10base-t mau receiver receive input impedance z in --22k w differential squelch threshold v ds 300 420 585 mv
LXT972 preliminary test specifications 39 table 24: 10base-t link integrity timing characteristics parameter sym min typ max units test conditions time link loss receive t ll 50 C 150 ms C link pulse t lp 2C7link pulses C link min receive timer t lr m in 2C7 ms C link max receive timer t lr m ax 50 C 150 ms C link transmit period t lt 8C24 ms C link pulse width t lpw 60 C 150 ns C 1. typical values are at 25 c and are for design aid only; not guaranteed and not subject to production testing.
LXT972 3.3v dual-speed fast ethernet transceiver 40 timing diagrams figure 23: 100base-tx receive timing - 4b mode t4 t5 t3 t6 t7 0ns 250ns crs rx_dv rxd<3:0> rx_clk col t1 t2 tpi table 25: 100base-tx receive timing parameters - 4b mode parameter sym min typ 1 max units 2 test conditions rxd<3:0>, rx_dv, rx_er setup to rx_clk high t1 10 C C ns C rxd<3:0>, rx_dv, rx_er hold from rx_clk high t2 10 C C ns C crs asserted to rxd<3:0>, rx_dv t3 3 C 5 bt C receive start of j to crs asserted t4 12 C 16 bt C receive start of t to crs de-asserted t5 10 C 17 bt C receive start of j to col asserted t6 16 C 22 bt C receive start of t to col de-asserted t7 17 C 20 bt C 1. typical values are at 25 c and are for design aid only; not guaranteed and not subject to production testing. 2. bt is the duration of one bit as transferred to and from the mac and is the reciprocal of the bit rate. 100base-t bit time = 10 -8 s or 10 ns.
LXT972 preliminary test specifications 41 figure 24: 100base-tx transmit timing - 4b mode t1 t2 t5 t3 t4 0ns 250ns txclk tx_en txd<3:0> tpo crs table 26: 100base-tx transmit timing parameters - 4b mode parameter sym min typ 1 max units 2 test conditions txd<3:0>, tx_en, tx_er setup to tx_clk high t1 12 C C ns C txd<3:0>, tx_en, tx_er hold from tx_clk high t2 0 C C ns C tx_en sampled to crs asserted t3 20 C 24 bt C tx_en sampled to crs de-asserted t4 24 C 28 bt C tx_en sampled to tpo out (tx latency) t5 5.3 C 5.7 bt C 1. typical values are at 25 c and are for design aid only; not guaranteed and not subject to production testing. 2. bt is the duration of one bit as transferred to and from the mac and is the reciprocal of the bit rate. 100base-t bit time = 10 -8 s or 10 ns.
LXT972 3.3v dual-speed fast ethernet transceiver 42 figure 25: 10base-t receive timing table 27: 10base-t receive timing parameters parameter sym min typ 1 max units 2 test conditions rxd, rx_dv, rx_er setup to rx_clk high t1 10 C C ns C rxd, rx_dv, rx_er hold from rx_clk high t2 10 C C ns C tpip/n in to rxd out (rx latency) t3 5.8 C 6.0 bt C crs asserted to rxd, rx_dv, rx_er asserted t4 5 C 32 bt C rxd, rx_dv, rx_er de-asserted to crs de-asserted t5 0.3 C 0.5 bt C tpi in to crs asserted t6 2 C 28 bt C tpi quiet to crs de-asserted t7 6 C 10 bt C tpi in to col asserted t8 1 C 31 bt C tpi quiet to col de-asserted t9 5 C 10 bt C 1. typical values are at 25 c and are for design aid only; not guaranteed and not subject to production testing. 2. bt is the duration of one bit as transferred to and from the mac and is the reciprocal of the bit rate. 10base-t bit time = 10 -7 s or 100 ns. rx_clk rxd, rx_dv, rx_er crs tpi t 3 t 4 t 2 t 6 t 1 t 7 t 5 col t 8 t 9
LXT972 preliminary test specifications 43 figure 26: 10base-t transmit timing table 28: 10base-t transmit timing parameters parameter sym min typ 1 max units 2 test conditions txd, tx_en, tx_er setup to tx_clk high t1 10 C C ns C txd, tx_en, tx_er hold from tx_clk high t2 0 C C ns C tx_en sampled to crs asserted t3 C 2 C bt C tx_en sampled to crs de-asserted t4 C 1 C bt C tx_en sampled to tpo out (tx latency) t5 C 72.5 C bt C 1. typical values are at 25 c and are for design aid only; not guaranteed and not subject to production testing. 2. bt is the duration of one bit as transferred to and from the mac and is the reciprocal of the bit rate. 10base-t bit time = 10 -7 s or 100 ns. tx_clk txd, tx_en, tx_er crs tpo t 1 t 3 t 4 t 5 t 2
LXT972 3.3v dual-speed fast ethernet transceiver 44 figure 27: 10base-t jabber and unjabber timing table 29: 10base-t jabber and unjabber timing parameters parameter sym min typ 1 max units test conditions maximum transmit time t1 20 C 150 ms C unjab time t2 250 C 750 ms C 1. typical values are at 25 c and are for design aid only; not guaranteed and not subject to production testing. txd col t 1 t 2 tx_en figure 28: 10base-t sqe (heartbeat) timing table 30: 10base-t sqe timing parameters parameter sym min typ 1 max units test conditions col (sqe) delay after tx_en off t1 0.65 C 1.6 us C col (sqe) pulse duration t2 0.5 C 1.5 us C 1. typical values are at 25 c and are for design aid only; not guaranteed and not subject to production testing. tx_clk tx_en t 1 t 2 col
LXT972 preliminary test specifications 45 figure 29: auto negotiation and fast link pulse timing figure 30: fast link pulse timing tpo t1 t1 t2 t3 clock pulse data pulse clock pulse tpo t4 t5 flp burst flp burst table 31: auto negotiation and fast link pulse timing parameters parameter sym min typ 1 max units test conditions clock/data pulse width t1 C 100 C ns C clock pulse to data pulse t2 55.5 C 63.8 m sC clock pulse to clock pulse t3 123 C 127 m sC flp burst width t4 C 2 C ms C flp burst to flp burst t5 8 12 24 ms C clock/data pulses per burst C 17 C 33 ea C 1. typical values are at 25 c and are for design aid only; not guaranteed and not subject to production testing.
LXT972 3.3v dual-speed fast ethernet transceiver 46 figure 31: mdio input timing t1 mdc mdio t2 figure 32: mdio output timing t3 mdc mdio t4 table 32: mdio timing parameters parameter sym min typ 1 max units test conditions mdio setup before mdc, sourced by sta t1 10 C C ns C mdio hold after mdc, sourced by sta t2 5 C C ns C mdc to mdio output delay, source by phy t3 C C 150 ns C mdc period t4 125 C C ns mdc = 8 mhz 1. typical values are at 25 c and are for design aid only; not guaranteed and not subject to production testing.
LXT972 preliminary test specifications 47 figure 33: power-up timing t1 vcc mdio,etc v1 table 33: power-up timing parameters parameter sym min typ 1 max units test conditions voltage threshold v1 C 2.9 C v C power up delay 2 t1 C C 300 m sC 1. typical values are at 25 c and are for design aid only; not guaranteed and not subject to production testing. 2. power up delay is specified as a maximum value because it refers to the phy's guaranteed performance - the phy will come out of reset after a delay of no more than 300 m s . system designers should consider this as a minimum value - after threshold v1 is reached, the mac should delay no less than 300 m s before accessing the mdio port. figure 34: reset pulse width and recovery timing t2 reset mdio,etc t1 table 34: reset pulse width and recovery timing parameters parameter sym min typ 1 max units test conditions reset pulse width t1 10 C C ns C reset recovery delay 2 t2 C C 300 m sC 1. typical values are at 25 c and are for design aid only; not guaranteed and not subject to production testing. 2. reset recovery delay is specified as a maximum value because it refers to the phy's guaranteed performance - the phy will com e out of reset after a delay of no more than 300 m s . system designers should consider this as a minimum value - after de-asserting reset*, the mac should delay no less than 300 m s before accessing the mdio port.
LXT972 3.3v dual-speed fast ethernet transceiver 48 register definitions the LXT972 register set includes multiple 16-bit registers. refer to table 35 for a complete register listing. ? base registers (0 through 8) are defined in accordance with the reconciliation sublayer and media independent interface and physical layer link signaling for 10/100 mbps auto-negotiation sections of the ieee 802.3 standard. ? additional registers are defined in accordance with the ieee 802.3 standard for adding unique chip functions. table 35: register set address register name bit assignments 0 control register refer to table 37 on page 51 1 status register #1 refer to table 38 on page 52 2 phy identification register 1 refer to table 39 on page 53 3 phy identification register 2 refer to table 40 on page 53 4 auto-negotiation advertisement register refer to table 41 on page 54 5 auto-negotiation link partner base page ability register refer to table 42 on page 55 6 auto-negotiation expansion register refer to table 43 on page 56 7 auto-negotiation next page transmit register refer to table 44 on page 57 8 auto-negotiation link partner received next page register refer to table 45 on page 57 9 1000base-t/100base-t2 control register not implemented 10 1000base-t/100base-t2 status register not implemented 15 extended status register not implemented 16 port configuration register refer to table 46 on page 58 17 status register #2 refer to table 47 on page 59 18 interrupt enable register refer to table 48 on page 60 19 interrupt status register refer to table 49 on page 61 20 led configuration register refer to table 50 on page 62 21- 29 reserved 30 transmit control register refer to table 51 on page 64
LXT972 register definitions 49 table 36: register bit map reg title bit fields addr b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 control register control reset loopback speed select a/n enable power down isolate re-start a/n duplex mode col test speed select reserved 0 status register status 100base- t4 100base- x full duplex 100base- x half duplex 10mbps full duplex 10mbps half duplex 100base- t2 full duplex 100base- t2 half duplex extended status reserved mf preamble suppress a/n complete remote fault a/n ability link status jabber detect extended capability 1 phy id registers phy id 1 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 2 phy id2 phy id no mfr model no mfr rev no 3 auto-negotiation advertisement register a/n advertise next page reserved remote fault reserved asymm pause pause 100base- t4 100base- tx full duplex 100base- tx 10base-t full duplex 10base-t ieee selector field 4 auto-negotiation link partner base page ability register a/n link ability next page ack remote fault reserved asymm pause pause 100base- t4 100base- tx full duplex 100base- tx 10base-t full duplex 10base-t ieee selector field 5 auto-negotiation expansion register a/n expansion reserved base page parallel detect fault link partner next page able next page able page received link partner a/n able 6 auto-negotiation next page transmit register a/n next page txmit next page reserved message page ack 2 toggle message / unformatted code field 7 auto-negotiation link partner next page receive register a/n link next page next page ack message page ack 2 toggle message / unformatted code field 8 configuration register port config reserved force link pass txmit disable bypass scrambler (100tx) reserved) jabber (10t) sqe (10t) tp loopback (10t) crs select (10t) reserved pre_en reserved reserved alternate next page reserved 16
LXT972 3.3v dual-speed fast ethernet transceiver 50 status register #2 status register #2 reserved 10/100 mode transmit status receive status collision status link duplex mode auto-neg auto-neg complete reserved polarity pause error reserved reserved 17 interrupt enable register interrupt enable reserved reserved auto-neg mask speed mask duplex mask link mask reserved reserved interrupt enable test interrupt 18 interrupt status register interrupt status reserved reserved auto-neg done speed change duplex change link change reserved md interrupt reserved reserved 19 led configuration register led config led1 led2 led3 led freq pulse stretch reserved 20 transmit control register trans. control reserved transmit low pwr port rise time control reserved 30 table 36: register bit map C continued reg title bit fields addr b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0
LXT972 register definitions 51 table 37: control register (address 0) bit name description type 1 default 0.15 reset 1 = phy reset 0 = normal operation r/w sc 0 0.14 loopback 1 = enable loopback mode 0 = disable loopback mode r/w 0 0.13 speed selection 0.6 0.13 speed selected r/w note 2 1 1 0 0 1 0 1 0 reserved 1000 mbps (not supported) 100 mbps 10 mbps 0.12 auto-negotiation enable 1 = enable auto-negotiation process 0 = disable auto-negotiation process r/w note 2 0.11 power-down 1 = power-down 0 = normal operation r/w 0 0.10 isolate 1 = electrically isolate phy from mii 0 = normal operation r/w 0 0.9 restart auto-negotiation 1 = restart auto-negotiation process 0 = normal operation r/w sc 0 0.8 duplex mode 1 = full duplex 0 = half duplex r/w note 2 0.7 collision test 1 = enable col signal test 0 = disable col signal test r/w 0 0.6 speed selection 0.6 0.13 speed selected r/w 0 1 1 0 0 1 0 1 0 reserved 1000 mbps (not supported) 100 mbps 10 mbps 0.5:0 reserved write as 0, ignore on read r/w 00000 1. r/w = read/write ro = read only sc = self clearing 2. default value of bits 0.12, 0.13 and 0.8 are determined by the led/cfg pins (refer to table 8 on page 16 ).
LXT972 3.3v dual-speed fast ethernet transceiver 52 table 38: mii status register #1 (address 1) bit name description type 1 default 1.15 100base-t4 not supported 1 = phy able to perform 100base-t4 0 = phy not able to perform 100base-t4 ro 0 1.14 100base-x full- duplex 1 = phy able to perform full-duplex 100base-x 0 = phy not able to perform full-duplex 100base-x ro 1 1.13 100base-x half- duplex 1 = phy able to perform half-duplex 100base-x 0 = phy not able to perform half-duplex 100base-x ro 1 1.12 10 mbps full-duplex 1 = phy able to operate at 10 mbps in full-duplex mode 0 = phy not able to operate at 10 mbps full-duplex mode ro 1 1.11 10 mbps half-duplex 1 = phy able to operate at 10 mbps in half-duplex mode 0 = phy not able to operate at 10 mbps in half-duplex ro 1 1.10 100base-t2 full- duplex not supported 1 = phy able to perform full-duplex 100base-t2 0 = phy not able to perform full-duplex 100base-t2 ro 0 1.9 100base-t2 half- duplex not supported 1 = phy able to perform half duplex 100base-t2 0 = phy not able to perform half-duplex 100base-t2 ro 0 1.8 extended status 1 = extended status information in register 15 0 = no extended status information in register 15 ro 0 1.7 reserved 1 = ignore when read ro 0 1.6 mf preamble sup- pression 1 = phy will accept management frames with preamble sup- pressed 0 = phy will not accept management frames with preamble suppressed ro 0 1.5 auto-negotiation complete 1 = auto-negotiation complete 0 = auto-negotiation not complete ro 0 1.4 remote fault 1 = remote fault condition detected 0 = no remote fault condition detected ro/lh 0 1.3 auto-negotiation ability 1 = phy is able to perform auto-negotiation 0 = phy is not able to perform auto-negotiation ro 1 1.2 link status 1 = link is up 0 = link is down ro/ll 0 1.1 jabber detect 1 = jabber condition detected 0 = jabber condition not detected ro/lh 0 1.0 extended capability 1 = extended register capabilities 0 = basic register capabilities ro 1 1. ro = read only ll = latching low lh = latching high
LXT972 register definitions 53 table 39: phy identification register 1 (address 2) bit name description type 1 default 2.15:0 phy id number the phy identifier composed of bits 3 through 18 of the oui. ro 0013 hex 1. ro = read only table 40: phy identification register 2 (address 3) bit name description type 1 default 3.15:10 phy id number the phy identifier composed of bits 19 through 24 of the oui. ro 011110 3.9:4 manufacturers model number 6 bits containing manufacturers part number. ro 001110 3.3:0 manufacturers revision number 4 bits containing manufacturers revision number. ro 0001 1. ro = read only figure 35: phy identifier bit mapping 0 00000 0 0 00 0001001101111000111000 abc rs x 15 0 15 10 9 4 3 0 00 the level one oui is 00207b hex phy id register #1 (address 2) = 0013 phy id register #2 (address 3) manufacturers model number revision number organizationally unique identifier 00 20 7b 5030
LXT972 3.3v dual-speed fast ethernet transceiver 54 table 41: auto negotiation advertisement register (address 4) bit name description type 1 default 4.15 next page 1 = port has ability to send multiple pages. 0 = port has no ability to send multiple pages. r/w 0 4.14 reserved ignore. ro 0 4.13 remote fault 1 = remote fault. 0 = no remote fault. r/w 0 4.12 reserved ignore. r/w 0 4.11 asymmetric pause pause operation defined in clause 40 and 27. r/w 0 4.10 pause 1 = pause operation enabled for full-duplex links. 0 = pause operation disabled. r/w note 2 4.9 100base-t4 1 = 100base-t4 capability is available. 0 = 100base-t4 capability is not available. (the LXT972 does not support 100base-t4 but allows this bit to be set to advertise in the auto-negotiation sequence for 100base-t4 operation. an external 100base-t4 transceiver could be switched in if this capability is desired.) r/w 0 4.8 100base-tx full-duplex 1 = port is 100base-tx full-duplex capable. 0 = port is not 100base-tx full-duplex capable. r/w note 3 4.7 100base-tx 1 = port is 100base-tx capable. 0 = port is not 100base-tx capable. r/w note 3 4.6 10base-t full-duplex 1 = port is 10base-t full-duplex capable. 0 = port is not 10base-t full-duplex capable. r/w note 3 4.5 10base-t 1 = port is 10base-t capable. 0 = port is not 10base-t capable. r/w note 3 4.4:0 selector field, s<4:0> <00001> = ieee 802.3. <00010> = ieee 802.9 islan-16t. <00000> = reserved for future auto-negotiation development. <11111> = reserved for future auto-negotiation development. unspecified or reserved combinations should not be transmitted. r/w 00001 1. r/w = read/write ro = read only 2. default value of bit 4.10 is determined by pin 33/h8. 3. default values of bits 4.5, 4.6, 4.7, and 4.8 are determined by led/cfg n pins at reset. refer to table 8 for details.
LXT972 register definitions 55 table 42: auto negotiation link partner base page ability register (address 5) bit name description type 1 default 5.15 next page 1 = link partner has ability to send multiple pages. 0 = link partner has no ability to send multiple pages. ro n/a 5.14 acknowledge 1 = link partner has received link code word from LXT972. 0 = link partner has not received link code word from the LXT972. ro n/a 5.13 remote fault 1 = remote fault. 0 = no remote fault. ro n/a 5.12 reserved ignore. ro n/a 5.11 asymmetric pause pause operation defined in clause 40 and 27. 1 = link partner is pause capable. 0 = link partner is not pause capable. ro n/a 5.10 pause 1 = link partner is pause capable. 0 = link partner is not pause capable. ro n/a 5.9 100base-t4 1 = link partner is 100base-t4 capable. 0 = link partner is not 100base-t4 capable. ro n/a 5.8 100base-tx full-duplex 1 = link partner is 100base-tx full-duplex capable. 0 = link partner is not 100base-tx full-duplex capable. ro n/a 5.7 100base-tx 1 = link partner is 100base-tx capable. 0 = link partner is not 100base-tx capable. ro n/a 5.6 10base-t full-duplex 1 = link partner is 10base-t full-duplex capable. 0 = link partner is not 10base-t full-duplex capable. ro n/a 5.5 10base-t 1 = link partner is 10base-t capable. 0 = link partner is not 10base-t capable. ro n/a 5.4:0 selector field s<4:0> <00001> = ieee 802.3. <00010> = ieee 802.9 islan-16t. <00000> = reserved for future auto-negotiation development. <11111> = reserved for future auto-negotiation development. unspecified or reserved combinations shall not be transmitted. ro n/a 1. ro = read only
LXT972 3.3v dual-speed fast ethernet transceiver 56 table 43: auto negotiation expansion (address 6) bit name description type 1 default 6.15:6 reserved ignore on read. ro 0 6.5 base page this bit indicates the status of the auto-negotiation variable, base page. it flags synchronization with the auto-negotiation state dia- gram allowing detection of interrupted links. this bit is only used if bit 16.1 (alternate np feature) is set. 1 = basepage = true 0 = basepage = false ro/ lh 0 6.4 parallel detection fault 1 = parallel detection fault has occurred. 0 = parallel detection fault has not occurred. ro/ lh 0 6.3 link partner next page able 1 = link partner is next page able. 0 = link partner is not next page able. ro 0 6.2 next page able 1 = local device is next page able. 0 = local device is not next page able. ro 1 6.1 page received 1 = indicates that a new page has been received and the received code word has been loaded into register 5 (base pages) or register 8 (next pages) as specified in clause 28 of 802.3. this bit will be cleared on read. if bit 16.1 is set, the page received bit will also be cleared when mr_page_rx = false or transmit_disable = true. ro lh 0 6.0 link partner a/n able 1 = link partner is auto-negotiation able. 0 = link partner is not auto-negotiation able. ro 0 1. ro = read only lh = latching high
LXT972 register definitions 57 table 44: auto negotiation next page transmit register (address 7) bit name description type 1 default 7.15 next page (np) 1 = additional next pages follow 0 = last page r/w 0 7.14 reserved write as 0, ignore on read ro 0 7.13 message page (mp) 1 = message page 0 = unformatted page r/w 1 7.12 acknowledge 2 (ack2) 1 = will comply with message 0 = can not comply with message r/w 0 7.11 toggle (t) 1 = previous value of the transmitted link code word equalled logic zero 0 = previous value of the transmitted link code word equalled logic one r/w 0 7.10:0 message/unfor- matted code field r/w 0000000 0001 1. ro = read only. r/w = read/write table 45: auto negotiation link partner next page receive register (address 8) bit name description type 1 default 8.15 next page (np) 1 = link partner has additional next pages to send 0 = link partner has no additional next pages to send ro 0 8.14 acknowledge (ack) 1 = link partner has received link code word from LXT972 0 = link partner has not received link code word from LXT972 ro 0 8.13 message page (mp) 1 = page sent by the link partner is a message page 0 = page sent by the link partner is an unformatted page ro 0 8.12 acknowledge 2 (ack2) 1 = link partner complies with the message 0 = link partner can not comply with the message ro 0 8.11 toggle (t) 1 = previous value of the transmitted link code word equalled logic zero 0 = previous value of the transmitted link code word equalled logic one ro 0 8.10:0 message/unfor- matted code field user definable ro 0 1. ro = read only.
LXT972 3.3v dual-speed fast ethernet transceiver 58 table 46: configuration register (address 16, hex 10) bit name description type 1 default 16.15 reserved write as zero, ignore on read. r/w 0 16.14 force link pass 1 = force link pass 0 = normal operation r/w 0 16.13 transmit disable 1 = disable twisted pair transmitter 0 = normal operation r/w 0 16.12 bypass scrambler (100base-tx) 1 = bypass scrambler and descrambler 0 = normal operation r/w 0 16.11 reserved ignore r/w 0 16.10 jabber (10base-t) 1 = disable jabber correction 0 = normal operation r/w 0 16.9 sqe (10base-t) 1 = enable heart beat 0 = disable heart beat r/w 0 16.8 tp loopback (10base-t) 1 = disable tp loopback during half-duplex operation 0 = normal operation r/w 0 16.7 crs select (10base-t) 1 = crs deassert extends to rx_dv deassert 0 = normal operation r/w 1 16.6 reserved write as zero, ignore on read. r/w 0 16.5 pre_en preamble enable. 0 = set rx_dv high coincident with sfd. 1 = set rx_dv high and rxd = preamble when crs is asserted. r/w 0 16.4:3 reserved write as zero, ignore on read. r/w 00 16.2 reserved write as zero, ignore on read. r/w 0 16.1 alternate np feature 1 = enable alternate auto negotiate next page feature. 0 = disable alternate auto negotiate next page feature r/w 0 16.0 reserved write as zero, ignore on read. r/w 0 1. r/w = read /write, lhr = latches high on reset
LXT972 register definitions 59 table 47: status register #2 (address 17) bit name description type 1 default 17.15 reserved always 0. ro 0 17.14 10/100 mode 1 = LXT972 is operating in 100base-tx mode. 0 = LXT972 is not operating 100base-tx mode. ro 0 17.13 transmit status 1 = LXT972 is transmitting a packet. 0 = LXT972 is not transmitting a packet. ro 0 17.12 receive status 1 = LXT972 is receiving a packet. 0 = LXT972 is not receiving a packet. ro 0 17.11 collision status 1 = collision is occurring. 0 = no collision. ro 0 17.10 link 1 = link is up. 0 = link is down. ro 0 17.9 duplex mode 1 = full-duplex. 0 = half-duplex. ro 0 17.8 auto-negotiation 1 = LXT972 is in auto-negotiation mode. 0 = LXT972 is in manual mode. ro 0 17.7 auto-negotiation complete 1 = auto-negotiation process completed. 0 = auto-negotiation process not completed. this bit is only valid when auto negotiate is enabled, and is equivalent to bit 1.5. ro 0 17.6 reserved reserved. ro 0 17.5 polarity 1 = polarity is reversed. 0 = polarity is not reversed. ro 0 17.4 pause 1 = device pause capable. 0 = device not pause capable. ro 0 17:3 error 1 = error occurred (remote fault, x,y,z). 0 = no error occurred. ro 0 17:2 reserved always 0. ro 0 17:1 reserved always 0. ro 0 17.0 reserved always 0. ro 0 1. ro = read only. r/w = read/write
LXT972 3.3v dual-speed fast ethernet transceiver 60 table 48: interrupt enable register (address 18) bit name description type 1 default 18.15:9 reserved write as 0; ignore on read. r/w n/a 18.8 reserved write as 0; ignore on read. r/w 0 18.7 anmsk mask for auto negotiate complete 1 = enable event to cause interrupt. 0 = do not allow event to cause interrupt. r/w 0 18.6 speedmsk mask for speed interrupt 1 = enable event to cause interrupt. 0 = do not allow event to cause interrupt. r/w 0 18.5 duplexmsk mask for duplex interrupt 1 = enable event to cause interrupt. 0 = do not allow event to cause interrupt. r/w 0 18.4 linkmsk mask for link status interrupt 1 = enable event to cause interrupt. 0 = do not allow event to cause interrupt. r/w 0 18.3 reserved write as 0, ignore on read. r/w 0 18.2 reserved write as 0, ignore on read. r/w 0 18.1 inten 1 = enable interrupts. 0 = disable interrupts. r/w 0 18.0 tint 1 = force interrupt on mdint . 0 = normal operation. r/w 0 1. r/w = read /write
LXT972 register definitions 61 table 49: interrupt status register (address 19, hex 13) bit name description type 1 default 19.15:9 reserved ignore ro n/a 19.8 reserved ignore ro 0 19.7 andone auto negotiation status 1 = auto negotiation has completed. 0 = auto negotiation has not completed. ro/sc n/a 19.6 speedchg speed change status 1 = a speed change has occurred since last reading this register. 0 = a speed change has not occurred since last reading this register. ro/sc 0 19.5 duplexchg duplex change status 1 = a duplex change has occurred since last reading this register. 0 = a duplex change has not occurred since last reading this register. ro/sc 0 19.4 linkchg link status change status 1 = a link change has occurred since last reading this register. 0 = a link change has not occurred since last reading this register. ro/sc 0 19.3 reserved ignore ro 0 19.2 mdint 1 = mii interrupt pending. 0 = no mii interrupt pending. ro 19.1 reserved ignore. ro n/a 19.0 reserved ignore ro 0 1. r/w = read/write, sc = self clearing.
LXT972 3.3v dual-speed fast ethernet transceiver 62 table 50: led configuration register (address 20, hex 14) bit name description type 1 default 20.15:12 led1 programming bits 0000 = display speed status (continuous, default) 0001 = display transmit status (stretched) 0010 = display receive status (stretched) 0011 = display collision status (stretched) 0100 = display link status (continuous) 0101 = display duplex status (continuous) 0110 = unused 0111 = display receive or transmit activity (stretched) 1000 = test mode- turn led on (continuous) 1001 = test mode- turn led off (continuous) 1010 = test mode- blink led fast (continuous) 1011 = test mode- blink led slow (continuous) 1100 = display link and receive status combined 2 (stretched) 3 1101 = display link and activity status combined 2 (stretched) 3 1110 = display duplex and collision status combined 4 (stretched) 3 1111 = unused r/w 0000 20.11:8 led2 programming bits 0000 = display speed status 0001 = display transmit status 0010 = display receive status 0011 = display collision status 0100 = display link status (default) 0101 = display duplex status 0110 = unused 0111 = display receive or transmit activity 1000 = test mode- turn led on 1001 = test mode- turn led off 1010 = test mode- blink led fast 1011 = test mode- blink led slow 1100 = display link and receive status combined 2 (stretched) 3 1101 = display link and activity status combined 2 (stretched) 3 1110 = display duplex and collision status combined 4 (stretched) 3 1111 = unused r/w 0100 1. r/w = read /write ro = read only lh = latching high 2. link status is the primary led driver. the led is asserted (solid on) when the link is up. the secondary led driver (receive or activity) causes the led to change state (blink). 3. combined event led settings are not affected by pulse stretch bit 20.1. these display settings are stretched regardless of t he value of 20.1. 4. duplex status is the primary led driver. the led is asserted (solid on) when the link is full duplex. collision status is the secondary led driver. the led changes state (blinks) when a collision occurs. 5. values are relative approximations. not guaranteed or production tested.
LXT972 register definitions 63 20.7:4 led3 programming bits 0000 = display speed status 0001 = display transmit status 0010 = display receive status (default) 0011 = display collision status 0100 = display link status 0101 = display duplex status 0110 = unused 0111 = display receive or transmit activity 1000 = test mode- turn led on 1001 = test mode- turn led off 1010 = test mode- blink led fast 1011 = test mode- blink led slow 1100 = display link and receive status combined 2 (stretched) 3 1101 = display link and activity status combined 2 (stretched) 3 1110 = display duplex and collision status combined 4 (stretched) 3 1111 = unused r/w 0010 20.3:2 ledfreq 5 00 = stretch led events to 30 ms. 01 = stretch led events to 60 ms. 10 = stretch led events to 100 ms. 11 = reserved. r/w 00 20.1 pulse- stretch 0 = disable pulse stretching of all leds. 1 = enable pulse stretching of all leds. r/w 1 20.0 reserved ignore. r/w n/a table 50: led configuration register (address 20, hex 14) C continued bit name description type 1 default 1. r/w = read /write ro = read only lh = latching high 2. link status is the primary led driver. the led is asserted (solid on) when the link is up. the secondary led driver (receive or activity) causes the led to change state (blink). 3. combined event led settings are not affected by pulse stretch bit 20.1. these display settings are stretched regardless of t he value of 20.1. 4. duplex status is the primary led driver. the led is asserted (solid on) when the link is full duplex. collision status is the secondary led driver. the led changes state (blinks) when a collision occurs. 5. values are relative approximations. not guaranteed or production tested.
LXT972 3.3v dual-speed fast ethernet transceiver 64 table 51: transmit control register #2 (address 30) bit name description type 2 default 30.15:11 reserved ignore r/w 0 30.12 transmit low power 1 = forces the transmitter into low power mode. also forces a zero-differential transmission. 0 = normal transmission. r/w 0 30.11:10 port rise time control 1 00 = 2.7 ns (default is pins txslew<1:0>) 01 = 3.5 ns 10 = 2.3 ns 11 = 2.0 ns r/w n/a 30.9:0 reserved ignore r/w 0 1. values are relative approximations. not guaranteed or production tested. 2. r/w = read/write
LXT972 package specification 65 package specification figure 36: LXT972 lqfp package specifications d d 1 a 1 a 2 l a b l 1 q 3 q 3 q e e 1 e / 2 e 64-pin low profile quad flat pack ? part number - LXT972lc commercial temperature range (0oc to +70oc) dim millimeters min max a C 1.60 a 1 0.05 0.15 a 2 1.35 1.45 b0.170.27 d 11.85 12.15 d 1 9.9 10.1 e 11.85 12.15 e1 9.9 10.1 e0.50 bsc 1 l0.450.75 l 1 1.00 ref q 3 11 o 13 o q 0 o 7 o 1. basic spacing between centers
LXT972 3.3v dual-speed fast ethernet transceiver 66 revision history table 52: changes from rev 1.0 to rev 1.1 (02/00) section page type description table 2 LXT972 mii signal description 6 modify change first sentence under mddis to read: when mddis is high, the mdio is disabled from read and write operations. twisted-pair interface 11 modify modify first and third paragraphs for greater clarify. mdio management interface 12 add add third paragraph regarding mdio and mddis operation in hardware control mode. figure 5 initialization sequence 14 modify modify figure to reflect change in mdio operation in the hard- ware control mode when mddis is set high. figure 8 10base-t clocking 19 modify remove (externally sourced) from figure. figure 9 10base-x clocking 19 modify remove (externally sourced) from figure. figure 21 typical tp interface - switch 20 modify add bypass cap to output transformer center tap. figure 22 typical tp interface - nic 21 modify add bypass cap to output transformer center tap. table 27 10base-t receive timing parameters 42 modify change min, typ, and max values for t3. table 28 10base-t transmit timing parameters 43 modify change typ value for t5.
LXT972 notes 67 notes
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